Optimize performance for non-amd64 architectures #3

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opened 2025-12-28 18:13:28 +00:00 by sami · 0 comments

sami commented

2025-12-28 18:13:28 +00:00

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Originally created by @fyrchik on GitHub (Jun 28, 2021).

Currently we have optimized versions only for AVX/AVX2-enabled architectures. While pure Go implementation also exists, we might want to optimize implementation for ARM or RISC-V architectures. Note that reference implementation from https://github.com/srijs/hwsl2-core deliberately implements only AVX* optimisations, so we must craft ARM/RISC-V code ourselves.

The first step is to optimize GF127 code (with our modulo) in isolation.
Comparing assembly output for pure Go and C version might be helpful.

Some links to study:
https://www.ssrc.ucsc.edu/Papers/greenan-mascots08.pdf

RISC-V has crypto-extensions as well, some of them might be useful:
https://riscv.org/wp-content/uploads/2017/12/Wed-1354-RISCV-CryptoExtensions-RichardNewell.pdf

Originally created by @fyrchik on GitHub (Jun 28, 2021). Currently we have optimized versions only for AVX/AVX2-enabled architectures. While pure Go implementation also exists, we might want to optimize implementation for ARM or RISC-V architectures. Note that reference implementation from https://github.com/srijs/hwsl2-core deliberately implements only AVX* optimisations, so we must craft ARM/RISC-V code ourselves. The first step is to optimize GF127 code (with our modulo) in isolation. Comparing assembly output for pure Go and C version might be helpful. Some links to study: https://www.ssrc.ucsc.edu/Papers/greenan-mascots08.pdf RISC-V has crypto-extensions as well, some of them might be useful: https://riscv.org/wp-content/uploads/2017/12/Wed-1354-RISCV-CryptoExtensions-RichardNewell.pdf